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Control of III-V Nucleation on Nanopatterned Silicon

Stage: Development

Due to epitaxially grown III-V semiconductors’ (III-Vs’) superlative optoelectronic properties, III-Vs are an attractive alternative for traditional Si-based semiconductors. Solar PV and LED technologies in particular could benefit from the enhanced quantum efficiencies of III-V devices. One approach for semiconductor heterojunctions with III-V materials is to grow III-V compounds atop Si. However, high-quality growth has remained challenging because of material incompatibilities of III-Vs and Si. Due to the lattice-constant mismatch and resulting changes in material polarity, a monatomic step on a (001)-Si surface results in antiphase boundaries (APBs) in the III-V film. This APB defect may be electrically active and likely acts as recombination center, which would reduce the quality and performance of a semiconductor device. The National Renewable Energy Laboratory presents a method to mitigate APBs by growth of III-Vs exclusively on silicon’s (111) crystallographic plane.



Scientists at the National Renewable Energy Laboratory have developed a method to grow III-V semiconductors (III-Vs) on Si substrates without APBs using a simplified manufacturing process. The method adjusts growth parameters such as temperature, V/III ratio, and pre-growth annealing under appropriate hydride environments to direct nucleation exclusively on one crystallographic plane of a nanopatterned silicon wafer for high-quality III-V semiconductors on Si. By controlling the growth temperature and V/III ratio, both GaP and GaAs can be nucleated exclusively on the (111) surface exposed by the grooves. These parameters direct the growth of high-quality III-V materials without the formation of stacking faults, eliminating the need for methods to remove the faults from subsequent growth and greatly simplifying design, cost, and scalability of the process.


Work thus far has used organometallic vapor phase epitaxy (OMVPE) to nucleate III-Vs; however, in principle, any growth technique can be used. Atomic-scale steps on (111)-surfaces do not generate APBs, so growth in grooves is more robust against APB formation than techniques developed to reduce APB formation on (001)-surfaces. Introducing significant process complexity, (001)-surface-growth techniques require non-equilibrium surface treatments, which have exhibited issues of consistency, scalability, and transferability between different reactors. Importantly, mechanisms for nucleation and coalescence on the disclosed grooved templates are fundamentally different than on traditional polished wafers. III-V growth in grooved Si wafers has been used already to produce state-of-the-art III-V-on-Si lasers as well as III-V-on-Si solar cells.


To learn more about the Control of III-V Nucleation on Nanopatterned Silicon, please contact Bill Hadley at:


bill.hadley@nrel.gov


ROI 19-126.

Applications and Industries

  • PV cell manufacturers
  • LED manufacturers
  • Other semiconductor manufacturers

Benefits

  • A robust growth method for high-quality III-V semiconductors on silicon with few antiphase boundary defects
  • A method to reduce significantly the numbers of other defects, dislocations, and disclinations in III-V semiconductors
  • A single-step growth procedure to simplify manufacturing design, reduce cost, and enhance process scalability